1. Field of the Invention
The present invention relates to an apparatus and method for the control of a phase-locked-loop motor drive system using a phase accumulator. The system allows high resolution velocity control of a commodity integrated brushless DC motor assembly designed for single speed operation with very minor modification.
2. Description of the Prior Art
Various brushless DC (BLDC) motors have been considered for use in laser printers. One such BLDC is particularly cost effective and includes drivers and speed control circuitry on a circuit board that is integrated into the motor assembly. The circuit includes a crystal controlled oscillator that runs at a constant frequency. The governed speed of the motor is directly related to the frequency of the controlled oscillator and is therefore also constant.
In such a laser printer, the motor speed is varied precisely to achieve better print registration than can be achieved in fixed speed printing systems. Such higher print registration is required by customers, particularly those using high resolution modes and those using preprinted forms applications. A fixed-speed motor would be unacceptable. However, it is desirable to use a motor that is derived from the existing fixed-speed motor with minor modifications to take advantage of the cost effectiveness of the fixed-speed motor while simultaneously getting the benefit of speed control.
The crystal oscillator in these motors runs typically at a frequency of several megahertz. Such a clock signal is then typically divided down to form a reference frequency for a phase-locked loop (PLL). This reference frequency is then compared in the PLL to a feedback frequency which is typically either a signal from an encoder attached to the rotor of the motor or a signal generated from the voltage induced by the permanent magnets of the motor as they pass over circuit traces etched into a nearby circuit board. The frequency division is carried out by a binary counter which, for example, may have from 10 to 14 stages, thus dividing by factors varying from 1,024 to 16,384.
One can control the speed of the motor described above by replacing the fixed signal from the crystal oscillator with a signal whose effective frequency can be varied. The motor speed will then be proportional to the clock frequency. The new signal could be supplied to the motor from an external source. Thus, the only required change to existing, single-speed commodity BLDC motor assemblies is the replacement of the on-board fixed frequency crystal or oscillator circuit with an off-board signal connection.
The resolution of the control achievable by the variable frequency is limited by the resolution of the source of the clock signal. When the speed needs to be controlled accurately, it becomes difficult to derive proper frequencies from the clock signals that are available in typical motor controllers.
Various methods have been used in the past to obtain high-resolution velocity control of DC and BLDC motor systems.
The most common approach utilized in DC motor control systems is to provide a low frequency reference clock to the PLL. For example, such an arrangement has been used in Lexmark's mirror motor control systems for both the 4039 and Optra printers. In such a system, either discrete motor drivers are used, or a motor driver capable of receiving a low frequency reference must be used. However, either of these approaches may be significantly more expensive, depending on the motor frequency, torque required, and various other system considerations.
An earlier approach to providing a variable high speed reference is described in U.S. Pat. No. 4,271,382 to Maeda et al. In the Maeda et al system, the output clock frequency is usually equal to half of the input crystal frequency. Occasionally, however, the output clocks may be suppressed for a number of cycles to slow the average clock rate. Alternatively, the output clocks may occasionally be switched from the divide-by-two of the input crystal to the input crystal itself, having the effect of speeding the average clock rate. In either case, the speed correction is performed at a rate equal to the rate of the reference frequency observed by the PLL. Such a clock-clobbering/clock-insertion approach produces an irregular waveform which would subject the motor system to serious frequency perturbations (i.e. jitter) during ramp-up and ramp-down times. In addition, switching the clock of a synchronous digital system onto the output waveform is inherently prone to creating glitches on the output which may be a problem for EMC and might be observed as a false additional clock by the subsequent logic.
Another approach to performing precise speed control of a BLDC motor is to generate a low frequency reference clock using conventional dividers from a crystal-based clock, and to use a frequency multiplier PLL circuit to generate a high frequency signal which is locked to the low frequency reference. The high frequency reference is then used as the reference input to a motor control system. Such a type of dual-PLL system has been implemented in commercially available integrated circuits, but not in an integrated package with the necessary drive electronics. Therefore, a system built around the dual-PLL will have a higher number of components.